1. Field of the Invention
The present invention relates to a display panel driving apparatus used in a typical plasma display panel (PDP).
2. Discussion of the Background
FIG. 1 shows a typical three-electrode surface-discharge type PDP.
As shown in FIG. 1, address electrode lines A1, A2, . . . , Am, dielectric layers 102 and 110, Y-electrode lines Y1, . . . , Yn, X-electrode lines X1, . . . , Xn, a fluorescent layer 112, partition walls 114, and a protection layer 104 are provided between front and rear glass substrates 100 and 106.
The address electrode lines A1, A2, . . . , Am are formed on the rear glass substrate 106 and covered by a lower dielectric layer 110. The partition walls 114 are formed on the lower dielectric layer 110 and in parallel with the address electrode lines A1, A2, . . . , Am. The partition walls 114 partition discharge areas in, and prevent optical interferences between, the display cells. The fluorescent layer 112 is formed on the lower dielectric layer 110 and the sides of the partition walls 114.
The Y-electrode lines Y1, . . . , Yn and the X-electrode lines X1, . . . , Xn, are formed on the front glass substrate 100, and they are arranged substantially orthogonally to the address electrode lines A1, A2, . . . , Am. Each intersection of an address electrode line and an X and Y electrode line pair establishes corresponding display cells. The Y-electrode lines Y1, . . . , Yn and the X-electrode lines X1, . . . , Xn may comprise transparent electrode lines Xna and Yna, which may be made from a transparent conductive material such as an indium tin oxide (ITO) film, and metallic electrode lines Xnb and Ynb, which increase electrode conductivity. The upper dielectric layer 102 covers the Y-electrode lines Y1, . . . , Yn and the X-electrode lines X1, . . . , Xn. The protection layer 104, which is typically a MgO layer, covers the upper dielectric layer 102 and protects the panel 1 from a strong electric field. A sealed discharge space 108 has a gas for generating plasma.
A typical driving method for such a PDP may include several operations such as sequentially performed reset, address, and sustain periods in each unit subfield. In the reset is period, all display cells are provided with uniform charge conditions. In the address period, the charge conditions of selected and non-selected display cells are established. In the sustain period, a display discharge is performed in the selected display cells to generate plasma, which emits ultraviolet light, thereby exciting the fluorescent layer 112 of the display cells to emit light.
FIG. 2 illustrates a typical driving apparatus for the PDP shown in FIG. 1.
A typical PDP 1 driving apparatus includes an image processing unit 200, a logic control circuit 202, an address driver 206, an X-driver 208, and a Y-driver 204. The image processing unit 200 converts an external image signal into internal image signals, such as 8 bit data representing red, green, and blue colors, a clock signal, and vertical and horizontal synchronization signals. The logic control circuit 202 generates driving control signals SA, SY, and SX according to the internal image signal from the image processing unit 200. The address driver 206 processes the address signal SA to generate and apply display data signals to the address electrode lines. The X-driver 208 processes the X-driving control signal SX and applies it to the X-electrode lines X1, . . . , Xn. The Y-driver 204 processes the Y-driving control signal SY and applies it the Y-electrode lines Y1, . . . , Yn.
U.S. Pat. No. 5,541,618 discloses an address-display separation driving method that may be used to drive the PDP 1.
FIG. 3 shows a typical address-display separation method for driving the Y-electrode lines shown in FIG. 1.
A unit frame may be divided into a plurality of subfields, (e.g., 8 subfields SF1, SF8), to implement a time division gradation display. Each subfield SF1, . . . , SF8 may be further divided into a reset period (not shown), an address period A1, . . . , A8, and a sustain period S1, . . . , S8.
In each address period A1, . . . , A8, display data signals may be applied to the address electrode lines A1, A2, . . . , Am in FIG. 1, and, simultaneously, corresponding scanning pulses may be applied to respective Y-electrode lines Y1, . . . , Yn.
In each sustaining period S1, . . . , S8, display discharge pulses may be alternately applied to the Y-electrode lines Y1, . . . , Yn and the X-electrode lines X1, . . . , Xn to generate a display discharge in the selected discharge cells.
A PDP's luminance is proportional to the number of sustaining pulses occupying the sustaining periods S1, . . . , S8 in a unit frame. As shown in FIG. 3, a frame forming one image may be represented by 8 subfields and 256 gradation levels, where different numbers of sustaining pulses are allocated to each subfield at a rate of 1 T, 2 T, 4 T, 8 T, 16 T, 32 T, 64 T, and 128 T, where T is a unit of time. Therefore, for example, to obtain a luminance corresponding to a gradation level of 133, cells may be addressed and sustain discharged during a period including SF1, SF3, and SF8.
The number of sustaining discharges allocated to each subfield may vary according to weights of the subfields based on an automatic power control (APC) operation. Additionally, they may be modified considering gamma characteristic or panel characteristics. For example, a gradation level allocated to SF4 may be decreased from 8 to 6, and a gradation level allocated to SF6 may be increased from 32 to 34. Furthermore, the number of subfields forming one frame may be modified as required.
FIG. 4 is a timing chart showing driving signals that may applied to the address electrodes A1:Am, the common electrodes X1:Xn, and the scanning electrodes Y1:Yn in a subfield SFn according to an address display separated (ADS) driving method of an AC PDP. The subfield SFn includes a reset period PR, an address period PA, and a sustain period PS.
In the reset period PR, reset pulses may be applied to all groups of scanning lines generate a writing discharge and initialize wall charge states of all panel cells so that they have similar wall charge conditions. In the subsequent address period PA, display cells may be selected by applying a bias voltage Ve to the common electrode X1:Xn and simultaneously turning on the scanning electrodes Y1:Yn and the address electrodes A1:Am. In the following sustain period PS, the sustaining pulse Vs may be alternately applied to the common electrode X1:Xn and the scanning electrode Y1:Yn while applying a ground voltage to the address electrodes A1:Am.
FIG. 5 is a timing chart showing another example of driving signals that may be applied to the PDP 1 shown in FIG. 1. Unlike FIG. 4, FIG. 5 shows a high level voltage VSC-H of the scanning electrode, in the address period PA, that is less than a low level sustaining voltage, e.g., a ground voltage.
However, in order to implement such wave form signals, a conventional circuit may require expensive and complicated components. The present invention provides simplified and less expensive driving circuits.